Analog Performance Benchmark in Nanometer CMOS
Daeik Kim, Jonghae Kim, Choongyeun Cho, and Jean-Olivier Plouchart
IBM Academy of Technology Conference on Analog Design, Technology, Models, and Tools 2008, May 2008
Abstract
The linkage between the technology and the product becomes loose, as CMOS technology scales down deeply and the product complexity multiplies with parallelism. Especially analog blocks have been under scrutiny due to yield issues, and they need to be monitored systematically by implementing a bridge between the technology and analog circuits. ; An analog performance benchmark (APB) as a counter part and complement of digital logic performance benchmark is proposed. The challenge and opportunity of the analog benchmark lies in the diversity of analog designs. The designs differ in the device types and size, layout style, topology, hierarchy, and interconnections.; The benchmark activity requires intense interaction between the product and the technology. The benchmark vehicles are defined by extracting common factors across the existing designs. Due to the limited resource, the APB takes a bottom-up approach, and the device and layout styles are set by the technology. The APB tries to de-embed basic analog function blocks, such as current mirror, CML buffer, and CML ring-oscillator, hierarchically. The benchmark devices, circuits, and metrics are presented. With the APB, the technology owns the anchor points to maximize product the yield and to examine the circuit behavior closely. The designer will be brought in to the benchmark and technology development process. The APB engagement opens a way to integrate foundry – fabless collaboration, which is compatible with the world-wide trend.; The first sets of APB structures have been implemented in 32nm and 45nm SOI nodes. The designers’ feedback and engagement would be essential to the development of the APB methodology.
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