CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement
Daeik Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski, and David Ahlgren
IEEE Custom Integrated Circuits Conference (CICC) 2006, Sept. 2006 Page(s):365 - 368
DOI: 10.1109/CICC.2006.320950
Abstract
A mixed-signal circuit performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process variations. A current-controlled oscillator frequency and the device threshold voltages are cross-correlated using simulation and RF measurement. Up to 93.9% cross correlation between oscillation frequency and device threshold voltage, and strong model-tohardware correlation are observed through the statistical analyses of simulation result and circuit measurement. Yield learning process of design, simulation, measurement, and statistical analysis is proposed.Download
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