A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology (invited)
Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, and Daihyun Lim
IEEE Compound Semiconductor IC Symposium (CSICS) 2008, Oct 2008
Abstract
A 5-stage CML prescaler operating up to 84GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.4fJ powerdelay product per gate. The phase noise degeneration at the sensitivity boundary of the CML static divider is reported for the first time.Download
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