A 5 GHz 11-Stage CML VCO with 40% Frequency Tuning in 0.13um SOI CMOS
Daeik D. Kim, Choongyeun Cho, and Jonghae Kim
Silicon Monolithic Integrated Circuits and RF Systems (SiRF) 2009, Jan 2009
Abstract
This paper presents a manufacturable CML-based 11-stage VCO for digital system clock fabricated in 0.13um SOI CMOS. The 11-stage design enables quality oscillation, wide frequency tuning range, and process variability rejection. On average, the VCO exhibits 40% frequency tuning range from 4.23 to 6.35GHz. The VCO phase noise is -129.8dBc/Hz at 10MHz offset in a current-controlled measurements, and average FoMT(10%) is -178.1dBc/Hz. Full 200mm wafer scan result is presented along the phase noise measurement to demonstrate a statistical methodology.Download
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