A 75GHz PLL Front-End Integration in 65nm SOI CMOS Technology
Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daihyun Lim, Weipeng Li, and Robert Trzcinski
IEEE Symposium on VLSI Circuits 2007, 14-16 June 2007 Page(s):174 - 175
DOI: 10.1109/VLSIC.2007.4342703
Abstract
A 75GHz PLL front-end composed of an inverter cross-coupled VCO, a buffer with ac coupling, and a static CML divider is integrated in 65nm SOI CMOS technology. The circuits are developed with milli-meter wave link specifications, technology consideration, process variation, and topology selections. The VCO observed at the divider output shows 5.9% frequency tuning range, centered at 73.4GHz. The VCO phase noise measured through the divider is -104dBc/Hz at 10MHz offset.Download
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