Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS
Daihyun Lim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daeik Kim, Robert Trzcinski, and Duane Boning
IEEE International Solid-State Circuits Conference (ISSCC) 2007, Feb. 2007 Page(s):542 - 621
DOI: 10.1109/ISSCC.2007.373534
Abstract
A static CML divide-by-two frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 100GHz with 52.4mW power dissipation. The self oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance and resistance.Download
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