FET layout optimization and variability in mmWave VCO and CML dividers in SOI CMOS
Jean-Olivier Plouchart, Daeik Kim, Sungjae Lee, Chuck Cho, and Jonghae Kim
IBM Academy of Technology Conference on Analog Design, Technology, Models, and Tools 2008, May 2008
Abstract
In modern SOI-CMOS technologies, the FET performance is very sensitive to the device geometry and layout. We found, trough modeling and experimenting that there are three important geometrical parameters that drive the FET Ft and Fmax. The first factor is the FET aspect ratio (Wfinger/Lpoly) that allows the designer to trade Ft and Fmax. The second parameter is the PC pitch and number of CA per diffusion which impact the mechanical stress, therefore the FET mobility and transconductance. The third is the near-FET resistor and capacitor wiring parasitic, which is dependant from the CA to PC distance, the number of CA per diffusion, and the different gate strapping strategies like M1 strapping and double gate sided contact. We found experimentally that for 12S, the peak-Ft PFET and NFET can be improved by 25% to a record 345 and 485GHz respectively. ; Theses FET optimization strategies were applied to the design of fundamental mmWave circuits for frequency generation, amplification and division. A static CML divide-by-two frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 100GHz with 52.4mW power dissipation. The divider self oscillation frequency is 92GHz with 0.57pJ switching energy. These CML Master-Slave latches were used to design a divide by 32 prescaler in 11S. A record maximum operating frequency of 84GHz was measured at 17.7mW/FF, and a power delay product of 26.4fJ.; A complementary LC-VCO is integrated in 65nm SOI, and statistically characterized on a 300mm wafer. Average center frequency is 67.9GHz, and frequency tuning range is 6.14GHz, or 9.05%. Maximum frequency is 73.5GHz, and maximum FTR is 6.68GHz. A phase noise at 10MHz offset is -106dBc/Hz, and power consumption is 5.37mW at 1.2V.; These benchmark circuits demonstrate that FET layout optimization is critical in order to scale circuit performance in non-scalable nm-CMOS technologies.; The high-speed analog benchmark circuits are also very sensitive to process variation and are therefore excellent test vehicle to understand the interaction between circuits and technology. For example for the CML-divider the measurement of the self-oscillation frequency at multiple bias conditions enables the estimation of the variation in threshold voltage, capacitance and resistance. Variation across a 300mm wafer of the self oscillation frequency is nearly 30%. Several wafers were measured, and by using a variant of principal component analysis, the systematic variation from die-to-die and wafer-to-wafer were analyzed and quantified. By using this new Constrained Principal Component Analysis, we can show that 65% of the divider mmWave self-oscillation frequency variation can be explained by the in-line data, and also that the process variation is substantially systematic. The statistical variation of the 68GHz LC-VCO was also quantified. We found experimentally, that the CML divider and LC-VCO frequency performances are not well correlated. This circuit mistracking between the VCO and divider can lead to PLL failure, and is therefore important to understand.
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