Manufacturable Parasitic-Aware Circuit-Level FETs in 65-nm SOI CMOS Technology
Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Robert Trzcinski, Sungjae Lee, Mahender Kumar, Christine Norris, Jae-Sung Rieh, Greg Freeman, and David Ahlgren
IEEE Electron Device Letters (EDL), June 2007 Page(s):520 - 522
DOI: 10.1109/LED.2007.897448
Abstract
This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency {T}$ of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum {T}$ of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.Download
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