Symmetric Vertical Parallel Plate Capacitors for On-chip RF Circuits in 65nm SOI Technology
Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Robert Trzcinski, Mahender Kumar, and Christine Norris
IEEE Electron Device Letters (EDL), July 2007 Page(s):616 - 618
DOI: 10.1109/LED.2007.899464
Abstract
This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and $-factor. An effective capacitance of 2.18 {fF}/muhbox{m}^{2}$ and a $-factor of 23.2 at 1 GHz are obtained from a 1x $+$ 2x (M1?M6) metal layer configuration's pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed.Download
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